Leeor Peled has over 20 years of experience developing CPU core architectures, starting at Intel working on various cores from Sandybridge, Ivybridge & Skylake, until Goldencove and Lioncove. He then moved to Huawei as a senior architect and research manager working on CPU cores for Mobile phones, server CPUs and many other domains. Leeor received his PhD at the Technion under Prof. Uri Weiser & Prof. Yoav Etsion.

Currently he is leading Huawei CPU Architecture Research with a team that spans across Israel, Zurich, Cambridge, Edinburgh, and China. His main focus is on Predictors, Parallelism, Caches, Software/Hardware codesign, System/OS, and dynamic optimization, but he may be willing to talk about other things if you’re not careful. He also serves as an associate editor of IEEE Computer Architecture Letters (CAL) and PC memeber on recent ISCA, Micro and HPCA conferences.

Fun fact: likes windsurfing :)

Areas of Interest

• CPU Architecture and Microarchitecture (uArch)
• Predictors, prefetchers and adaptive configurability
• Automated parallelism, code decomposition, speculative multithreading
• Code semantics inference and extrpolation
• Hardware-Software Codesign
• Memory Hierarchy: Prefetching and Cache Design, replacement policies
• Machine Learning for CPU optimization
• Performance evaluation, modeling and reliable benchmarking
• Binary translation and optimization (BT/DBO)
• Memory order models, transactional Memory

Publications (see extended version through tabs)

• 2026-11-01
  Micro 2026 (TBD) Exploiting Program Semantics for Hardware Prefetching

• 2026-11-01
  Micro 2026 (TBD) Enabling Adaptive Policy Arbitration with Context Awareness

• 2026-06-01
  ISCA 2026 Bumper: Hinting Instruction Usefulness for Robust Unified Caches

• 2026-02-01
  HPCA 2026 Tempranillo: Non-Speculative Early Register Release

• 2025-02-01
  HPCA 2025 To Cross or Not to Cross Pages for Prefetching?

• 2022-01-01
  arXiv Identifying and Exploiting Sparse Branch Correlations for Optimizing Branch Prediction

• 2019-06-01
  ACM Transactions on Architecture and Code Optimization (TACO) A Neural Network Prefetcher for Arbitrary Memory Access Patterns

• 2015-06-01
  ISCA 2015 Semantic Locality and Context-based Prefetching Using Reinforcement Learning

• 2025-01-01
  Patent Method and corresponding apparatus for filtering prefetch requests

• 2025
  Patent Efficient load value prediction based on program context and misprediction control mechanism for pipelined microprocessor designs

• 2024
  Patent Crash-consistent persistent memory devices and methods

• 2024
  Patent Function as a service (FaaS) system enhancements

• 2024
  Patent Apparatus method and system for ensuring quality of service for multi-threading processor cores

• 2023
  Patent Methods and apparatus to dynamically enable and/or disable prefetchers

• 2022
  Patent Method and computing arrangement for loading data into data cache from data memory

• 2022
  Patent An apparatus and method for performing enhanced pointer chasing prefetcher

• 2016
  Patent Branch Predictor with Branch Resolution Code Injection

• 2016
  Patent Pipelined Prefetcher for Parallel Advancement of Multiple Data Streams

• 2011
  Patent Systems apparatuses and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Employment

• 2005 - 2020: Performance Architect at Intel, focusing on CPU microarchitecture design and optimization

  

• 2020 - 2023: Senior Architect at Huawei (Toga Networks - Israel research center), head of Advanced Technologies Group (ATG)

• 2023 - 2026: Head of CPU Architecture Research at Huawei (Skyline CPU)

  

Invited talks

• Recent directions in CPU Architecture, talk at Bar-Ilan university [Link]
• DPC4 Talk, Full recording
• Future of CPU research in the agentic AI, Tech talks [Link]

Service

• Conferences:
  • CATC - Compilers, Architecture and Tools Conference (Co-organizer and Program Committee
  • Micro 56 - 56th IEEE/ACM International Symposium on Microarchitecture 2023 (Toronto) - Program committee
  • Micro 57 - 56th IEEE/ACM International Symposium on Microarchitecture 2024 (Austin) - Program committee
  • Micro 58 - 56th IEEE/ACM International Symposium on Microarchitecture 2025 (Seoul) - Program committee
  • ISCA 2016 - International Symposium on Computer Architecture (Seoul) - ERC
  • ISCA 2022 - 49th IEEE/ACM International Symposium on Computer Architecture (NY) - ERC
  • ISCA 2026 - 53rd IEEE/ACM International Symposium on Computer Architecture (Raleigh) - ERC
  • HPCA 2026 - 32st IEEE International Symposium on High-Performance Computer Architecture (Sydney) - Program committee
  • HPCA 2027 - 33st IEEE International Symposium on High-Performance Computer Architecture (Salt Lake City) - Program committee
  • DPC 4 - 4th Data Prefetching Championship (in conjunction with HPCA 2026) - Program committee,
• Journals:
  • Associate editor for IEEE Computer Architecture Letters (CAL)
  • Reviews for TC, TACO, CAL, ICSEE